An input receiver (e.g., a low voltage complementary metal oxide semiconductor (LVCMOS) receiver) downconverts an external signal (e.g., a pad signal) to feed the downconverted signal to the core of a semiconductor chip at a required voltage level. That is, the input receiver interfaces with the external signal at an input/output (I/O) supply voltage level and converts the external signal to the required voltage level. Currently, the input receiver employs an inverter or buffer like architecture which fixes its dc trip point based on the size of the input receiver. The dc trip point of the input receiver may be fixed at half the I/O supply voltage. Thus, if the external signal of the input receiver is greater than the dc trip point, then it is converted to the supply voltage level of the input receiver, whereas if the external signal is less than the dc trip point, then it is converted to zero voltage.
The arrangement may work well when the I/O supply voltage level (e.g., 1.8 volts) is equal or less than the maximum voltage (e.g., 1.8 volts) the transistors in the input receiver can sustain. However, for the I/O supply level (e.g., 2.5 volts or 3.3 volts) greater than the maximum voltage (e.g., 1.8 volts) the transistors can sustain, the design may stress the transistors, thus degrading the performance of the input receiver. For example, the design of the input receiver may have to be heavily skewed to meet the LVCMOS joint electron device engineering council (JEDEC) switching thresholds for higher supply voltages (e.g., 3.3 volts), and the distortion in the design of the input receiver may degrade the performance of the input receiver.
The performance degradation can be corrected by setting the dc trip point at the appropriate level. However, according to the current architecture of the input receiver, the trip point of the input receiver is determined by the components' size of the input receiver and/or the supply voltage level of input receiver. As a result, the inflexible nature of the input receiver in setting the dc trip point may hinder improving the performance of the input receiver.